The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, the scaling down of a pattern may cause an unsymmetrical pattern profile on an IC device. The unsymmetrical pattern may cause issues such as a non-correctable or uncontrollable pattern-to-pattern overlay error on the IC device. In another example, an accuracy of a lithography exposing tool is impacted when using a monitor wafer with an unsymmetrical pattern monitoring or calibrating the lithography exposing tool. Accordingly, what is needed is a method forming a more symmetrical pattern.